The present invention relates to a memory cell with a stored charge on its gate, a kind of so-called DRAM gain cell, and a process for the manufacture thereof.
A DRAM cell is composed of one transistor and one capacitor which can generally accomplish the minimum area among conventional RAM cells. With a design rule being finer, however, it is requested to develop a complicated capacitor structure and a new capacitor material for achieving a small area and a capacitance which a capacitor is required to attain. And, the cost of DRAM production is increasing due to the formation and processing of dielectric materials and electrode films, research and development of passivation techniques and introduction of novel manufacturing apparatus, and the cost of the capacitor production is now much more expensive than that the transistor production. Readout signals lessen as a finer semiconductor device is structured, and it is ultimately difficult to detect information stored in a memory cell without a change in structure and materials.
For overcoming the above problem, one DRAM gain cell is known in "Super-Low-Voltage Operation of a Semi-Static Complementary Gain DRAM Memory Cell", S. Shukuri, et al., 1993 Symposium on VLSI Technology, Digest of Tech. Papers, 3A-4, pp23-24, 1993. FIG. 40 shows an equivalent circuit of the above DRAM gain cell composed of a memory transistor RM having a floating gate and a complementary word transistor WM. In the DRAM gain cell, a gate of the word transistor WM and a gate of the memory transistor RM are connected to a common word line WL, and one source/drain region of the word transistor WM and one source/drain region of the memory transistor RM are connected to a common bit line BL, so that the number of external wiring is decreased. When information is written in the above DRAM gain cell, a voltage of 1.5 Volts is applied to the bit line BL, and a minus voltage is applied to the word line WL. As a result, a positive charge is stored on the floating gate of the memory transistor RM, and a gate threshold voltage of the memory transistor RM shifts toward a minus direction. When the DRAM gain cell is in a standby state, a potential is applied to the word line WL so that the memory transistor RM and the word transistor WM are not brought into an on-state. When information is read out, applied to the word line WL is a potential between the gate threshold voltage of the memory transistor RM when a positive charge is stored on the floating gate and the gate threshold voltage when no positive charge is stored. As a result, when a positive charge is stored on the floating gate, a current flows through the DRAM gain cell.
As explained above, the DRAM gain cell shown in FIG. 40 in principle requires no capacitor although it is required as an auxiliary in some cases. However, when it is attempted to decrease the area of the DRAM gain cell, the word transistor WM is required to be composed of a thin film transistor (TFT), and the problem is that the production process is complicated and that the DRAM gain cell can be no longer produced by a conventional production process. Further, there is another problem that controllability and reproducibility of TFTs are difficult when mass production technologies available at present are applied. Moreover, there is another problem that since the above DRAM gain cell has a small operation margin, it is required to connect the gates or the drains of the two transistors to different word lines or different bit lines for securing the operation margin, and that the area of such a DRAM gain cell cannot be decreased.